A high level modeling system (HLMS) is a software tool in which electronic designs can be described, simulated, and translated by machine into a design realization. An HLMS provides a higher level of abstraction for describing an electronic circuit than a hardware description language (HDL). An HLMS generally provides a mathematical representation of signals as compared to standard logic vectors in a hardware description language (HDL). The Xilinx System Generator tool for DSP is an example of an HLMS.
An HLMS for electronic circuit design generally offers abstractions that are not available in traditional HDLs. For example, an HLMS is likely to offer abstractions that relate to signal propagation and signal state, while an HDL may support a detailed representation that more closely models a realized electronic circuit.
An electronic design modeled in an HLMS may be viewed as a collection of blocks that communicate through signals, with the blocks being organized into levels of a hierarchy. Signals in an HLMS are discrete, time-varying sequences of values. An HLMS generally provides abstractions to support implementing synchronous designs without requiring the specification of explicit references to clocks or clock signals.
An HLMS generally supports testing and debugging of the high-level design, along with hardware generation of the high-level design. In the process of generating hardware, the HLMS compiles the high-level blocks into HDL components. Compilation may be slow and require a large amount of memory because the entire design must be considered for some compilation operations. For example, in the System Generator HLMS, a user may specify a VHDL entity name to be used for a black box. This forces the System Generator HLMS to examine the entire high-level design before assigning names.
The present invention may address one or more of the above issues.